Sigma delta modulators are well established for use in high resolution analog to digital conversion. Typically the filters in the sigma delta modulator have complex architectures and play important role in the resolution of these ADCs.
A block diagram of a first order sigma-delta modulator A/D system is shown in FIG. 1. The system consists of an analog sigma-delta modulator followed by a digital decimator. The modulator consists of an integrator, an internal A/D converter or quantizer, and a D/A converter (DAC) used in the feedback path. The process of noise shaping by the sigma-delta modulator can be viewed as pushing quantization noise power from the signal band to other frequencies. The modulator output is just a delayed version of the signal plus quantization noise that has been shaped. The modulator output can then be low-pass filtered to attenuate the out-of-band quantization noise and finally can be down sampled to the Nyquist rate.
Different Methods to Improve the Performance of Sigma-Delta ADCs
1-Over Sampling:
Over sampling reduces the quantization noise power in the signal band by spreading a fixed quantization noise power over a bandwidth much larger than the signal band. Disadvantages: this method is limited by the frequency constraint of sigma-delta ADCs. As an example for a signal with the bandwidth of W we have:
  OSR  ⁢          ⁢  £  ⁢          ⁢            f      max              2      ⁢      w      where fmax is the maximum frequency that can be supported by Sigma-Delta ADC.2-Higher-order SDMs
Higher orders Sigma-Delta modulators provide more quantization noise suppression over the low frequency signal band, and more amplification of the noise outside the signal band. Hence more noise power is pushed outside the signal band.
To obtain a performance improvement, these converters require analog circuits that need to be more complex and precise than those used in the 1st order sigma-delta modulator.
3-Multi-bit SDMs
The converters using a multi-bit internal quantizer offer more resolution from the internal quantizer. The use of a multi-bit quantizer affects the power of quantization noise in the expressions for the SNR, where each additional bit used in the quantizer will yield a 6 dB improvement in the SNR.
The main disadvantage is that the multi-bit DAC cannot be easily fabricated in VLSI with sufficient linearity needed for high resolution conversion. In addition, the multi-bit output also complicates the digital low-pass filter hardware following the modulator, because for multi-bit processing, the filter requires multi-bit hardware multipliers.
The previous methods were working more on some changes in the architecture of SDM ADCs to improve the performance of these ADCs, while the present invention proposes a method for applying a mathematical signal processing algorithm to improve the performance of these ADCs.
Therefore, it would advantageous to have a method and system that applies a mathematical signal processing algorithm to improve the performance of these ADCs.